The present invention relates to a charge coupled device, and particularly to an improvement of an output circuit thereof.
FIG. 1A shows a prior art output circuit of a charge coupled device (CCD). It includes a semiconductor substrate 1 of a first conductivity type, gate electrodes 2, 3 and 4, and high-concentration impurity regions or heavily impurity-doped regions 5 and 6 of a second conductivity type, different from the first conductivity type. Applied to the gate electrode 2 is one phase .phi.H of the drive clock. Applied to the gate electrode 3 is a DC voltage VGo. Applied to the gate electrode 4 is a reset clock .phi.R. The impurity region 6 is connected to a reset power supply VR. The impurity region 5 is called a floating diffusion and is electrically connected to a gate electrode of a source-follower output transistor Tro formed on the same substrate 1. The drain of the transistor Tro is connected to a source-follower power supply Vo. The source of the transistor Tro, constituting the output terminal Do, is connected through a load resistor Ro to the ground. The gate electrode 4, the floating diffusion 5, and the impurity region 6 forms a MOS transistor in which the floating diffusion 5 and the impurity region 6 constitute the drain and the source, respectively.
FIG. 2 shows clock signals applied to the output circuit of FIG. 1A, and FIGS. 1B to 1D show potentials at various parts (coresponding in vertical alignment between FIG. 1A and FIGS. 1B to 1D) of FIG. 1A at times t1 to t3 to FIG. 2.
At time t1 in FIG. 2, the clock .phi.H is high, a potential well is formed under the gate electrode 2, and a signal charge Q is stored, as shown in FIG. 1B. The clock oR is then high, and the MOS transistor Trt is on and the floating diffusion 5 and the gate electrode 4 of the transistor Tro is reset to Vro.
At time t2 in FIG. 2, the clock .phi.R has fallen low, the MOS transistor Trt has been turned off, as shown in FIG. 1C. When the clock .phi.R goes from high to low, the potential of the floating diffusion 5 is lowered due to capacitive coupling between the gate electrode 4 and the floating diffusion 5. While the clock .phi.R is low, the node connected to the floating diffusion 5 is floating.
At time t3 in FIG. 2, the clock .phi.H has fallen low, and the signal charge Q which has been stored in the potential well under the gate electrode 2 is transferred or injected to the floating diffusion 5, to change the mode potential of the floating diffusion 5, as shown in FIG. 1D. This potential change is read out by the source-follower transistor Tro.
The above-described output circuit has a problem in that a noise due to the on-resistance of the MOS transistor Trt is generated each time the floating diffusion 5 is reset. Details on such noises are described in an article, entitled "Two-Phase Charge-Coupled Devices with Overlapping Polysilicon and Aluminum Gates" by W. F. Kosonocky and J. E. Carnes, in RCA Review, Vol 34, March 1973, pp. 164 to 203.
The noise is called kTC noise, and is dependent on the capacitance of the floating diffusion 5. In the low signal range, this noise is the greatest factor determining the performance of the CCD. It is therefore desirable that this noise be eliminated or reduced to minimum.
A solution to this problem is a use of correlated double sampling as disclosed in an article entitled "Characterization of Surface Channel CCD Image Arrays at Low Light levels" by M. H. White, et al, in Journal of Solid-State Circuits, Vol. SC-9, No. 1, February 1974. But this arrangement requires high speed clocks.